1. Field of the Invention
The present invention generally relates to an apparatus and method of delay calculation for structured ASICs (application-specific integrated circuits). More specifically, the present invention is directed to delay calculation for ASICs incorporating clock circuits that used to distribute clock signals.
2. Description of the Related Art
Delay calculation is one of the most important techniques in integrated circuit design. Operating an integrated circuit at desired timings requires accurately estimating delay times of respective circuit components within the integrated circuit by delay calculation, and verifying operation timings of the integrated circuit on the basis of the estimated delay times. For instance, a delay time of a clock circuit integrated within the integrated circuit must be accurately estimated, and then clock skews must be verified as being appropriate on the basis of the estimated delay times. In addition, delay times of desired paths within the integrated circuit must be verified as being appropriate. Under such technical background, various sorts of delay calculation methods have been proposed.
One of the most typical delay calculation methods is a cell-library-based method, which uses a cell delay library describing delay times of respective kinds of cells (refer to, for example, JP-A-Heisei 11-259555). The cell-library-based method is directed to delay calculation of integrated circuits that adopt a cell-based design technique. The cell-library-based method uses a cell library that contains tables describing associations of input slews and/or load capacitances with delay times for respective kinds of cells. Delay times of respective cells integrated within the target integrated circuit are acquired by table lookup from the cell library, referring a netlist of the target integrated circuit. This is followed by delay calculation of desired paths based on the acquired delay times of the respective cells.
Delay calculation of integrated circuits incorporating macro circuits is also known in the art, for instance, in JP-A-Heisei 10-162040 and JP-A 2001-273338. In the known techniques, delay calculation of an integrated circuit incorporating macro circuits is achieved using a macro delay library containing: tables describing associations of delay times of boundary cells connected to input terminals of macro circuits with input slews of the boundary cells; tables describing associations of delay times of boundary cells connected to output terminals of macro circuits with input load capacitances of the boundary cells; and delay times among the boundary cells. Delay calculation for desired paths within the integrated circuit is performed using the delay times acquired from the macro delay library.
Another typical delay calculation method is an analog simulation method. SPICE is one of the most typical simulators for analog simulation. In the analog simulation, a target integrated circuit is expressed by a circuit model described by resistors, capacitors, coils, and other primitive elements, and delay times are calculated by solving the circuit equation corresponding to the circuit model. For instance, a document entitled “A Clock Distribution Circuit Layout Design Tool for Large-scale and High-Speed ASICs” written by Masayuki Terai et al., Institute of Japanese Information Processing, Volume 43, No. 5, Pages 1294 to 1303, May in 2002, discloses that SPICE-compatible circuit simulation is applied to analyze clock skew of a clock circuit within an ASIC.
The inventor of the present invention has discover the fact that delay calculations of clock circuits are wastefully repeated when the conventional delay calculation methods are applied to delay calculations of structured ASICs. Conventionally, every time an integrated circuit is designed, delay times of a clock circuit integrated within the integrated circuit are estimated. For instance, when two structured ASICs are designed, delay times of clock circuits within the respective ASICs are separately calculated. In accordance with investigations by the inventor, performing delay calculations of the clock circuits within the respective structured ASICs wastefully uses design resources, which may undesirably increase the TAT in designing structure ASICs.